The present invention generally relates to signal select circuits, and more particularly to a signal select circuit, which receives n input signals (n is an integer), and selects one of the n input signals in order of priority. Further, the present invention is concerned with a signal select control circuit, which controls a signal select circuit as described above.
Signal select circuits are widely used in signal processing devices. For example, a signal select circuit receives n input signals and selects one of the n input signals in order of a predetermined signal number respectively assigned to each of the n input signals. Examples of such signal processing devices are an exchange, which forms a synchronous communication network in a wire communication system, and a transmission device in the synchronous communication network. Conventionally, such signal processing devices use a single master clock generated by a clock signal source provided in common for the entire synchronous communication network. Recently, a communication network, which has a redundant structure including a plurality of clock signal sources, has been proposed in order to ensure the operation of the system if one of the clock signal sources has a failure. In this case, a priority order is determined beforehand in which one of the clock signal sources is selected when a failure occurs, so that one clock signal source, which has the highest priority, can be selected from among the clock signal sources, which are normally working. It should be noted that the setting of the priority order is based on various conditions, such as the system structure and the situation in which the system is provided. Thus, it is necessary to determine a plurality of priority orders in order to cope with the various conditions. For this purpose, conventionally, a plurality of signal select circuits are provided.
FIG. 1 is a block diagram of a system using a conventional signal select circuit. The system shown in FIG. 1 includes a priority-based select circuit 1 and a signal selector 2. Signals A1 - An show the states of respective n devices, such as clock signal sources. Each of the signals A1 - An has a logical value of "1" (valid) when the corresponding device is normally working, and has a logical value of "0" (invalid) when it has a failure. The signals A1 - An are input to the priority-based select circuit 1, which generates output signals B1 - Bn in response to the input signals A1 - An. The output signals B1 - Bn show, which one of the input signals A1 - An (n devices) should be selected in a predetermined priority order and show that the other input signals should not be selected. The output signals B1 - Bn are transmitted to and input by the signal selector 2, which receives signals S1 - Sn, which are subjected to a select operation executed by the signal selector 2. The signal selector 2 selects one of the signals S1 - Sn specified by the output signals B1 - Bn.
During operation, each of the input signals A1 - An is equal to "0" or "1". Assuming that "1" is a valid signal, the priority-based select circuit 1 sets one of the output signals B1 - Bn in response to valid signals out of the input signals A1 - An to be "1" in a predetermined priority order, and sets the other output signals to be "0".
FIG. 2 is a diagram showing the logical function, which forms the priority-based select operation executed by the priority-based select circuit 1. An upper block shown in FIG. 2 indicates the states of the input signals A1 - An, and a lower block shown therein indicates the states of the output signals B1 - Bn. The logical function shown in FIG. 2 is defined so that the priority becomes higher as the suffix of the input signals A1 - An becomes smaller (A1&gt;A2&gt;...&gt;An). In the columns of the upper block shown in FIG. 2, "1" shows a normal state, "0" shows an abnormal state, and "X" shows either "1" or "0" ("don't care"). In the columns of the lower block shown in FIG. 2, "1" means that the corresponding output signal should be selected and "0" means that it should not be selected.
The input signals A1 - An having the respective states defined at the first column correspond to the output signal B1 - Bn having the respective states defined at the first column. That is, the input signals A1 - An having the respective states defined at the ith column correspond to the output signal B1 - Bn having the respective states defined at the ith column. For example, when the input signal A1 indicates "0" (the corresponding clock signal source S1 has a failure) and the input signal A2 indicates "1", the output signals B1 - Bn defined at the second column are output by the priority-based select circuit 1. As shown in FIG. 2, only the output signal B2 indicates "1" and the other output signals B1 and B3 - Bn indicate "0". When the output signal B2 indicates "1", the select circuit 2 selects the corresponding clock signal source S2.
As described above, the logical function of the priority-based select circuit 1 is based on the priority order of A1&gt;A2&gt;...&gt;An, and is configured so that this priority order is realized. It should be noted that the priority order defined in the priority-based select circuit 1 is fixed. As has been described previously, it is required that the system having a signal priority circuit as described above can operate in different priority orders based on the various conditions. Thus, the conventional system shown in FIG. 1 cannot cope with the requirement of use of different priority orders.
In order to meet the above-mentioned requirement, a system shown in FIG. 3 has been proposed. As shown in FIG. 3, the system includes a plurality of priority-based select circuits 3-1, 3-2, ..., 3-m where m is an integer. Input signals A1-A5 (n=5) are respectively input to the priority-based select circuits 3-1 through 3-m. The input signals A1-A5 are arranged on the input side of each of the priority-based select circuits 3-1 through 3-m so that they are arranged in a priority order inherent in each of the priority-based select circuits 3-1 through 3-m. For example, the input signals A1-A5 on the input side of the priority-based select circuit 3-1 are arranged in a priority order of A1&gt;A2&gt;...&gt;A5, and the input signals A1-A5 on the input side of the priority-based select circuit 3-2 are arranged in a priority order of A2&gt;A1&gt;A3&gt;A4&gt;A5. Output signals of the priority-based select circuits 3-1 through 3-m are respectively input to a selector 4, which selects one of the output signals of the priority-based select circuits 3-1 through 3-m in accordance with a control signal Cf supplied from an external device. With the above-mentioned arrangement, it becomes possible to selectively use the m priority orders.
However, it is necessary to provide a plurality of priority-based select circuits, as described above. More specifically, when n input signal lines are used, there are a maximum of n! of priority orders, and thus n! priority-based select circuits may need to be provided. For example, when n=5, 120 (=5!) priority order circuits may need to be provided.